In this tutorial, we will have a brief introduction to MOSFET i.e., the Metal Oxide Semiconductor Field Effect Transistor. We will learn about different types of MOSFET (Enhancement and Depletion), its internal structure, an example circuit using MOSFET as a Switch and a few common applications.
Introduction
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Transistors, the invention that changed the World. They are semiconductor devices that act as either an electrically controlled switch or a signal amplifier. Transistors come a variety of shapes, sizes and designs but essentially, all transistors fall under two major families. They are:
- Bipolar Junction Transistors or BJT
- Field Effect Transistors or FET
To learn more about a basics of transistor and its history, read the Introduction to Transistors tutorial.
There are two main differences between BJT and FET. The first difference is that in BJT, both the majority and minority charge carriers are responsible for current conduction whereas in FETs, only the majority charge carriers are involved.
The other and very important difference is that a BJT is essentially a current controlled device meaning the current at the base of the transistor determines the amount of current flowing between collector and emitter. In case of a FET, the voltage at the Gate (a terminal in FET equivalent to Base in BJT) determines the current flow between the other two terminals.
FETs are again divided into two types:
- Junction Field Effect Transistor or JFET
- Metal Oxide Semiconductor Field Effect Transistor or MOSFET
Let us focus on MOSFET in this tutorial.
Metal Oxide Semiconductor FET
The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one type of FET transistor. In these transistors, the gate terminal is electrically insulated from the current carrying channel so that it is also called as Insulated Gate FET (IG-FET). Due to the insulation between gate and source terminals, the input resistance of MOSFET may be very high such (usually in the order of 1014 ohms.
Like JFET, the MOSFET also acts as a voltage controlled resistor when no current flows into the gate terminal. The small voltage at the gate terminal controls the current flow through the channel between the source and drain terminals. In present days, the MOSFET transistors are mostly used in the electronic circuit applications instead of the JFET.
MOSFETs also have three terminals, namely Drain (D), Source (S) and Gate (G) and also one more (optional) terminal called substrate or Body (B). MOSFETs are also available in both types, N-channel (NMOS) and P-channel (PMOS). MOSFETs are basically classified in to two forms. They are:
- Depletion Type
- Enhancement Type
- Channel Construction of MOSFET
Depletion Type
The depletion type MOSFET transistor is equivalent to a “normally closed” switch. The depletion type of transistors requires gate – source voltage (VGS) to switch OFF the device.
The symbols for depletion mode of MOSFETs in both N-channel and P-channel types are shown above. In the above symbols, we can observe that the fourth terminal (substrate) is connected to the ground, but in discrete MOSFETs it is connected to source terminal. The continuous thick line connected between the drain and source terminal represents the depletion type. The arrow symbol indicates the type of channel, such as N-channel or P-channel.
In this type of MOSFETs a thin layer of silicon is deposited below the gate terminal. The depletion mode MOSFET transistors are generally ON at zero gate-source voltage (VGS). The conductivity of the channel in depletion MOSFETs is less compared to the enhancement type of MOSFETs.
Enhancement Type
The Enhancement mode MOSFET is equivalent to “Normally Open” switch and these types of transistors require a gate-source voltage to switch ON the device. The symbols of both N-channel and P-channel enhancement mode MOSFETs are shown below.
Here, we can observe that a broken line is connected between the source and drain, which represents the enhancement mode type. In enhancement mode MOSFETs, the conductivity increases by increasing the oxide layer, which adds the carriers to the channel.
Generally, this oxide layer is called as ‘Inversion layer’. The channel is formed between the drain and source in the opposite type to the substrate, such as N-channel is made with a P-type substrate and P-channel is made with an N-type substrate. The conductivity of the channel due to electrons or holes depends on N-type or P-type channel respectively.
Structure of MOSFET
- The basic structure of the MOSFET is shown in the above figure. The construction of the MOSFET is very different when compared to the construction of the JFET. In both enhancement and depletion modes of MOSFETs, an electric field is produced by gate voltage, which changes the flow charge carriers, such as electrons for N-channel and holes for P-channel.
Here, we can observe that the gate terminal is situated on top of thin metal oxide insulated layer and two N-type regions are used below the drain and source terminals.
In the above MOSFET structure, the channel between drain and source is an N-type, which is formed opposite to the P-type substrate. It is easy to bias the MOSFET gate terminal for the polarities of either positive (+ve) or negative (-ve).
If there is no bias at the gate terminal, then the MOSFET is generally in non-conducting state so that these MOSFETs are used to make switches and logic gates. Both the depletion and enhancement modes of MOSFETs are available in N-channel and P-channel types.
Depletion Mode
The depletion mode MOSFETs are generally known as ‘Switched ON’ devices, because these transistors are generally closed when there is no bias voltage at the gate terminal. If the gate voltage increases in positive, then the channel width increases in depletion mode.
As a result the drain current ID through the channel increases. If the applied gate voltage more negative, then the channel width is very less and MOSFET may enter into the cutoff region. The depletion mode MOSFET is a rarely used type of transistor in the electronic circuits.
The following graph shows the Characteristic Curve of Depletion Mode MOSFET.
The V-I characteristics of the depletion mode MOSFET transistor are given above. This characteristic mainly gives the relationship between drain- source voltage (VDS) and drain current (ID). The small voltage at the gate controls the current flow through the channel.
The channel between drain and source acts as a good conductor with zero bias voltage at gate terminal. The channel width and drain current increases if the gate voltage is positive and these two (channel width and drain current) decreases if the gate voltage is negative.
Enhancement Mode
The Enhancement mode MOSFET is commonly used type of transistor. This type of MOSFET is equivalent to normally-open switch because it does not conduct when the gate voltage is zero. If the positive voltage (+VGS) is applied to the N-channel gate terminal, then the channel conducts and the drain current flows through the channel.
If this bias voltage increases to more positive then channel width and drain current through the channel increases to some more. But if the bias voltage is zero or negative (-VGS) then the transistor may switch OFF and the channel is in non-conductive state. So now we can say that the gate voltage of enhancement mode MOSFET enhances the channel.
Enhancement mode MOSFET transistors are mostly used as switches in electronic circuits because of their low ON resistance and high OFF resistance and also because of their high gate resistance. These transistors are used to make logic gates and in power switching circuits, such as CMOS gates, which have both NMOS and PMOS Transistors.
The V-I characteristics of enhancement mode MOSFET are shown above which gives the relationship between the drain current (ID) and the drain-source voltage (VDS). From the above figure we observed the behavior of an enhancement MOSFET in different regions, such as ohmic, saturation and cut-off regions.
MOSFET transistors are made with different semiconductor materials. These MOSFETs have the ability to operate in both conductive and non-conductive modes depending on the bias voltage at the input. This ability of MOSFET makes it to use in switching and amplification.
N-Channel MOSFET Amplifier
When compared to BJTs, MOSFETs have very low transconductance, which means the voltage gain will not be large. Hence, MOSFETs (for that matter, all FETs) are generally not used in amplifier circuits.
But, none the less, let us see a single-stage ‘class A’ amplifier circuit using N-Channel Enhancement MOSFET. The N-channel enhancement mode MOSFET with common source configuration is the mainly used type of amplifier circuit than others. The depletion mode MOSFET amplifiers are very similar to the JFET amplifiers.
The input resistance of the MOSFET is controlled by the gate bias resistance which is generated by the input resistors. The output signal of this amplifier circuit is inverted because when the gate voltage (VG) is high the transistor is switched ON and when the voltage (VG) is low then the transistor is switched OFF.
The general MOSFET amplifier with common source configuration is shown above. This is an amplifier of class A mode. Here the voltage divider network is formed by the input resistors R1 and R2 and the input resistance for the AC signal is given as Rin = RG = 1MΩ.
The equations to calculate the gate voltage and drain current for the above amplifier circuit are given below.
VG = (R2 / (R1 + R2))*VDD
ID = VS/ RS
Where,
VG = gate voltage
VS = input source voltage
VDD = supply voltage at drain
RS = source resistance
R1 & R2 = input resistors
The different regions in which the MOSFET operates in their total operation are discussed below.
Cut-off Region: If the gate-source voltage is less than the threshold voltage then we say that the transistor is operating in the cut-off region (i.e. fully OFF). In this region drain current is zero and the transistor acts as an open circuit.
VGS < VTH => IDS = 0
Ohmic (Linear) Region: If the gate voltage is greater than threshold voltage and the drain-source voltage lies between VTH and (VGS – VTH) then we say that the transistor is in linear region and at this state the transistor acts as a variable resistor.
VGS > VTH and VTH < VDS < (VGSVGS – VTH) => MOSFET acts as a variable Resistor
Saturation Region: In this region the gate voltage is much greater than threshold voltage and the drain current is at its maximum value and the transistor is in fully ON state. In this region the transistor acts as a closed circuit.
VGS >> VTH and (VGS – VTH) < VDS < 2(VGS – VTH) => IDS = MaximumThe gate voltage at which the transistor ON and starts the current flow through the channel is called threshold voltage. This threshold voltage value range for N-channel devices is in between 0.5V to 0.7V and for P-channel devices is in between -0.5V to -0.8V.
The behavior of a MOSFET transistor in depletion and enhancement modes depending on the gate voltage is summarized as follows.
| N-Channel Depletion | |||
| N-Channel Enhancement | |||
| P-Channel Depletion | |||
| P-Channel Enhancement |
Applications
- MOSFETs are used in digital integrated circuits, such as microprocessors.
- Used in calculators.
- Used in memories and in logic CMOS gates.
- Used as analog switches.
- Used as amplifiers.
- Used in the applications of power electronics and switch mode power supplies.
- MOSFETs are used as oscillators in radio systems.
- Used in automobile sound systems and in sound reinforcement systems.
Conclusion
A complete beginner’s guide to introduction of MOSFET. You learned the structure of a MOSFET, different types of MOSFET, their circuit symbols, an example circuit using a MOSFET to control an LED and also few areas of applications.
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Circuits that measure IDSS
It's not all there! What? Your parts manufacturer provides an incomplete IDSS range for your FET? Then he's telling you to go fish! What's a guy to do? You need some fishng gear. Homebrew an IDSS meter. Measure your FETs, instead of depending on incomplete datasheets. Sound good? Below are schematics for meters that reel in the data. |
♦ CAUTION. No enhancement devices. These circuits measure parameters for JFETS or depletion MOSFETs. But the circuits won't measure enhancement MOSFETs. If you plug in a MOSFET, it won't turn on. You might mistakenly assume that it's dead. (Examples: No 2N7000s! No BS170s!) |
About the meters
- Use your DVM for the ID ammeter and the VP(pinch-off voltage) voltmeter. The IDSS reading could vary from a few milliamps to about 100 mA. The power voltage that you use must exceed the FET's VP value.
- Your measurements apply to the device that you use, not the manufacturer's model. FETs of the same type vary greatly. (Sometimes nature intrudes upon science. FET characteristics are an example.) For this reason, your measurements probably won't agree with values on the manufacturer's datasheet. Fear not. Differing values don't indicate a defect.
- Battery considerations. IDSS-level drain current subjects your battery to the maximum current draw for the device. To preserve your battery, keep measurement periods brief. To measure P-channel devices, reverse the battery connections.
The simple meterBuild in minutes. Test in seconds! The simple IDSS meter (Figure 1) allows you to read IDSS. Depending on the FET you're measuring, IDSS could run anywhere from a few milliamps to 100 milliamps. (Very few FETs have an IDSS below 1 mA. Example: PN4117.) In this circuit, you may use a handheld multimeter to measure IDSS current. To find VGS (off), Malvino provides this handy formula (1.)... | Fig. 1. Simple IDSS meter |
VGS (off)= 2(IDSS) / GM0,
where GM0 is the transconductance at IDSS
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Why do I need to know VGS (off)? The pinch-off voltage VP is of the same magnitude (but opposite sign) as VGS (off). The all-important IDSS occurs at the pinch-off voltage VP. Voltage VP also defines the voltage boundaries of your amplifier design (the most and least current that the FET supports).
Using the simple meter. The table below shows the results of some tests by the author. On a solderless breadboard, the simple meter circuit went together quickly. The 2N3819 device under test was a U.S. Fairchild JFET, originally from Mouser (new-old stock). The 2N5457 device was a Chinese “Fairchild” JFET from eBay. The readings were low, perhaps because the power voltage was 9 volts, instead of the manufacturer-specified 15 volts. To check that hypothesis, further tests were necessary. A retest several days later produced the same IDSS values at 9 VDC. Under 15 VDC power, the IDSS currents remained the same as at 9 VDC power.
The parallel IDSS values moderated the author's earlier cynicism about datasheets. The datasheet's drain curves prescribed that the IDSS values would be the same at 9 or 15 volts. The test devices regulated the current as they should. The measured IDSS values also remained within spec.
| FET Type | Power Volts | IDSS (mA) | Test Date | Tester Type |
| 2N3819 | 9 | 10.96 | 8-11-2020 | Simple |
| 2N5457 | 9 | 2.56 | 8-11-2020 | Simple |
| 2N3819 | 9 | 11 | 8-20-2020 | Simple |
| 2N5457 | 9 | 3 | 8-20-2020 | Simple |
| 2N3819 | 15 | 12 | 8-20-2020 | Simple |
| 2N5457 | 15 | 3 | 8-20-2020 | Simple |
• NOTES & CONCLUSIONS
| ||||
The swanky meterTechnician's Cadillac. The swanky IDSS meter appears at Figure 2. You can use the power voltage (B2) of your choice. The 20-volt supply is a typical example. (DC power packs are fine, too. A particular FET might also require a larger battery B1. For example, Hayes and Horowitz use -15V. (2.)) | Fig. 2. Swanky IDSS meter (4.) |
To measure VGS (off), adjust the 10K pot. At some resistance value, the FET will cut off. When it does, ID will drop to zero. (Drain voltage VDS will also rise to the power voltage. (3.)) Now, measure VGS (off) between gate and ground. This circuit also allows you to plot the GM(transconductance) curve for the FET. (An example of this curve appears at Figure 5.)
♦ CAUTION: FIGURE 2. Never connect the gate battery B1 backwards! This battery must provide a zero to negative voltage to the gate. The voltage must never rise above zero volts. Otherwise, the gate junction could melt, destroying the JFET. |
Detailed instructions for the swanky meter
- Attach your DVM according to the schematic. (Connect the meter '+' lead to VDD. Connect the meter '-' lead to the drain terminal of the FET.)
- Adjust Pot VR1 so that it shorts the FET gate to the source. Current through the test FET will reach IDSS.
- Press TEST BUTTON S1. Current will flow through your DVM.
- While pressing the button, read IDSS on your DVM. For most small-signal FETs, the reading will be in milliamps. (Some FETS operate in the sub-milliamp region.)
- After taking the reading, release button S1.
- To read VGS (off), connect a second DVM across the gate and common. We'll call this DVM-2. (See the schematic, Figure 2.)
- Press TEST BUTTON S1. At ID (DVM-1) , no current is flowing through the FET channel. The drain-to-ground voltage equals VDD (9 volts).
- While pressing the button, read VGS on DVM-2. The reading will be in volts. The magnitude of this reading equals the pinch-off voltage VP. (Please ignore the sign. VP and VGS (off) use opposite signs.)
- After taking the reading, release button S1.
More About VP & IDSS
What is VP? VP, or more precisely, VP0, is the pinch-off voltage at IDSS. At VP0, the drain saturates with current. (5.) VP0 is equivalent to -1[VGS (off)]. (6.) See the drawing (right). What is IDSS? Looking at Figure 3, let's start at the origin, bottom-left. Moving right along the Y-axis, we spot VP, the pinch-off voltage. Here, we arrive at the vertical line. Now, we follow the line upward to the drain curve IDSS. Here, we see that VP points to the knee in the curve. At this point, the current through the FET flattens out. We've reached current saturation, or IDSS! | Fig. 3. IDSS occurs at pinch-off voltage VP. (7.) |
By “saturation,” we mean that the FET is passing the maximum current that it can safely handle. Going rightward from VP, the curve is flat. On the flat region, the FET operates as a constant current source. That is, drain voltage has almost no effect on drain current. (The device breakdown voltage is further to the right. At breakdown, the current rises exponentially. The device likely expires.) (8.)
Designing with Drain Curves
Flat section. On the device datasheet, there are more drain (ID) curves beneath the IDSS curve. Each drain curve has a saturation mode and a pinch-off voltage. We need the FET to operate on the flat, or “saturation mode” section of the curve. Select a drain curve. In design work, we can operate our FET on any drain curve. On Figure 4, right, the top drain curve is IDSS. Parallel to, and below IDSS are four horizontal curves. Each curve produces a different drain current ID. We identify these curves by the negative gate bias voltage VGS that produces them...
Deriving RS from GMSource resistor RS bias allows us to select a drain curve. RS bias reduces ID. A good, starting value for RS is (1 / GM). This statement assumes that we use the GM(transconductance) value at IDSS. (Datasheets sometimes refer to GM as GFS or YFS.) The datasheet provides GM as a range of values at IDSS. Yet we must choose only one GM value! We can cope by selecting an average or “typical” GM value. (Sometimes the manufacturer provides the typical value.) (10.) What is GM? There are two types of GM. Dynamic GM is the change in gate voltage that causes a given change in drain current. Static GM expresses the drain current per volt of gate voltage. The measurement is in amperes (or more likely milliamps). Yet we divide the ratio (mA / 1V) or (µA / 1V), expressing the result as a decimal number. The unit for this new term for inverse resistance is the Siemens, S (or U). Example: 3,000 µS or 3 mS. Both of these mean “3 milliamps per volt.” | Fig. 4. Drain family curves(9.) Fig. 5. GM curve: RS selects drain curve.(11.) Fig. 6. RS & static GM |
Source resistor connection. The reciprocal of any static GM value is a source resistor value. Malvino walks us through the easy RS formula. (12.) Be sure to ignore the VGS sign... RS= (-VGS / ID) RS examples. Figure 5 includes three examples of source resistors. The table below gives the calculations to find these three resistor values...
Tour of the GM Curve. At Figure 5, notice that transconductance (GM) is a parabola. As the curve ascends, the transconductance increases. As the curve descends, the transconductance decreases. Here's what this means for source resistor values: A large source resistor locks in a high reverse bias on the gate. With this gate voltage, the transconductance is low, but the current drain is economical. With this large resistor, be careful not to approach VGS (off) too closely, or the device might clip. A small source resistor allows far more drain current to flow. The transconductance is high, but the battery drain and heat might be excessive. A heat sink might be necessary. If the design approaches IDSS too closely, clipping could again become a problem. Consider the drain current of your circuit. Drain current affects the operating transconductance of the FET. Manufacturer specs usually give the transconductance figure at IDSS. Are you operating at a lower ID than IDSS? Then use a transconductance (GM) value that's less than the device maximum. Example: The manufacturer powers his model MPF102 at IDSS, 20 mA. But your project FET draws 2 mA, average. The datasheet GM range is 2 to 7.5 mS. You choose 2 mS, giving an RS of 500 ohms: (1 / 0.002)= 500Ω. You can then use a 470-ohm or 560-ohm standard resistor. |
VP & IDSS Summary
| Fig. 7. Operation zone for a FET amplifier, within the active area of the drain curves.(14.) |
- To use a lower ID (drain) curve, increase the source bias voltage, VGS. (With N-channel devices, make VGS more negative. For P-channel devices, more positive.)
- To use a higher curve, reduce the source bias voltage, VGS. (With N-channel devices, make VGS more positive. For P-channel devices, more negative.)
- For an N-channel device, VGS is negative. For a P-channel device, VGS is positive.
- The reverse-biased gate prevents gate current. No gate current flows. (15.)
- VP is a drain-source voltage.
- VGS (off) is a gate-source voltage. It has the same magnitude as Vp, but the opposite sign.
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Footnotes
1. Albert Paul Malvino, Ph.D., Transistor Circuit Approximations, 3rd ed. (New York: McGraw-Hill Book Company, 1980), 239. ▶Re: Formula for finding VDS (off).
2. Thomas C. Hayes & Paul Horowitz, The Art of Electronics Student Manual, 1st ed. (New York: Cambridge University Press, 1989), 156. ▶Re: Use of -15V power supply to bias VGS. Useful when reading VGS (off). Broader range than 6-volt circuit in Kybett & Boysen. (Refers to measurement of N-channel devices. P-channel devices require a +15V bias supply.)
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3. Harry Kybett & Earl Boysen, All New Electronics: Self-Teaching Guide, 3rd ed. (Indianapolis, IN: Wiley Publishing, Inc., 2008), 142. ▶Re: When there is no current flowing in the FET channel, VD rises to the power voltage VDD.
4. Ibid., 138. ▶Re: Schematic, circuit for measuring shorted gate drain current, IDSS & pinch-off voltage, VP.
5. Donald L. Schilling & Charles Belove, Electronic Circuits: Discrete and Integrated, 2nd ed. (New York: McGraw-Hill Book Company, 1979), 135. ▶Re: Term VP0, p. 136.
6. Malvino, 237. ▶Re: VP is VDS (off) without the sign.
7. Ibid., 235. ▶Re: Pinch-off curve diagram.
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8. Ibid., 235-236. ▶Re: Connection between pinch-off voltage, VP, & shorted gate drain current, IDSS
9. Ibid., 236. ▶Re: Four drain-family curves.
10. Ibid., 239, 242-244. ▶Re: Good starting value for RS is (1 / GM), 242-244. •GM = GFS or YFS, 239. •Datasheets usually list GM at IDSS, 242 & 244.
11. Ibid., 236. ▶Re: GM or transconductance curves show how the RS value selects the drain curve.
12. Ibid., 236. ▶Re: Formula #2 for RS value: RS= (-VGS / ID).
13. Ibid., 236. ▶Re: When VGS = 0, you achieve IDSS, maximum drain current.
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14. Ibid., 236. ▶Re: Operation zone for FET amplifier. The author drew the operation zone over a set of drain curves from Malvino.
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15. Schilling & Belove, 135. ▶Re: The reverse-biased gate prevents gate current.